View AD1862N-J_1929760.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

functional block diagram voltage reference input & digital offset 20-bit dac ad1862 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ? s ? s trim +v l clk data le ? l +v s nr 2 adj nr 1 agnd i out r f dgnd rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ultralow noise 20-bit audio dac ad1862* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features 120 db signal-to-noise ratio 102 db d-range performance 6 1 db gain linearity 6 1 ma output current 16-pin dip package 0.0012% thd + n applications high performance compact disc players digital audio amplifiers synthesizer keyboards digital mixing consoles high resolution signal processing product description the ad1862 is a monolithic 20-bit digital audio dac. each device provides a 20-bit dac, 20-bit serial-to-parallel input register and voltage reference. the digital portion of the ad1862 is fabricated with cmos logic elements that are pro- vided by analog devices bimos ii process. the analog por- tion of the ad1862 is fabricated with bipolar and mos devices as well as thin-film resistors. new design, layout and packaging techniques all combine to produce extremely high performance audio playback. the de- sign of the ad1862 incorporates a digital offset circuit which improves low-level distortion performance. low stress packag- ing techniques are used to minimize stress-induced parametric shifts. stress-sensitive circuit elements are located in die areas which are least affected by packaging stress. laser-trimming of initial linearity error affords extremely low total harmonic distortion. output glitch is also small, contributing to the over- all high level of performance. the noise performance of the ad1862 is excellent. when used with the recommended two external noise-reduction capacitors, it achieves 120 db signal-to-noise ratio. the serial input port consists of the clock, data and latch enable pins. a serial 20-bit, 2s complement data word is clocked into the dac, msb first, by the external data clock. a latch-enable signal transfers the input word from the internal serial input register to the dac input register. the data clock can function at 17 mhz, allowing 16 f s operation. the serial input port is compatible with second-generation digital filter chips for con- sumer audio products such as the npc sm5813 and sm5818. the ad1862 operates with 5 v to 12 v supplies for the dig- ital power supplies and 12 v supplies for the analog supplies. the digital and analog supplies can be separated for reduced digital crosstalk. separate analog and digital common pins are also provided. the ad1862 typically dissipates less than 300 mw. the ad1862 is packaged in a 16-pin plastic dip. the operating range is guaranteed to be C25 c to +70 c. product highlights 1. 120 db signal-to-noise ratio. (typical) 2. 102 db d-range performance. (minimum) 3. 1 db gain linearity @ C90 db amplitude. 4. 20-bit resolution provides 120 db of dynamic range. 5. 16 f s operation. 6. 0.0016% thd+n @ 0 db signal amplitude. (typical) 7. space saving 16-pin dip package. 8. 1 ma output current. *protected by u.s. patent numbers: 4,349,811; 4,857,862; 4,855,618; 3,961,326; 4,141,004; 4,902,959.
ad1862Cspecifications min typ max units resolution 20 bits digital inputs v ih 2.0 4.0 v v il 0.4 0.8 v i ih @ v ih = 4.0 v 1.0 m a i il @ v il = 0.4 v C10 m a maximum clock input frequency 17 mhz accuracy gain error 2 % midscale output error 2 5 m a total harmonic distortion + noise (eiaj) 1 0 db, 990.5 hz AD1862N-J C98 (0.0012) C96 (0.0016) db (%) ad1862n C94 (0.0019) C92 (0.0025) db (%) C20 db, 990.5 hz ad1862n, n-j C84 (0.0063) C80 (0.01) db (%) C60 db, 990.5 hz ad1862n, n-j C45 (0.56) C42 (0.8) db (%) d-range, C60 db, a-weight filter 102 db signal-to-noise ratio 2 : (eiaj) 1 a-weight filter AD1862N-J 113 119 db ad1862n 110 119 db gain linearity @ C90 db AD1862N-J 1db ad1862n 1db output current bipolar range 1ma tolerance 1 6 2 % output impedance ( 30%) 2.1 k w settling time 350 ns feedback resistor value 3k w tolerance 1 6 2 % power supply voltage v l and Cv l 4.75 12.0 13.2 v voltage v s and Cv s 10.8 12.0 13.2 v current +i, v l and v s = 12 v, 17 mhz clock 11 15 ma Ci, Cv l and Cv s = C12 v, 17 mhz clock 13 16 ma power dissipation v l and v s = 12 v, Cv l and Cv s = C12 v, 17 mhz clock 288 372 mw temperature range specification +25 c operation C25 +70 c storage C60 +100 c notes 1 test method complies with eiaj standard cp-307. 2 the signal-to-noise measurement includes noise contributed by the se5534a op amp used in the test fixture but does not include the noise contributed by the low pass filter used in the test fixture. specifications in boldface are tested on all production units at final electrical test. specifications subject to change without notice. rev. a C2C (t a at +25 8 c and 6 12 v supplies, see figure 10 for test circuit schematic)
ad1862 C3C rev. a 20 ?0 ?0 1 ?0 ?0 ?0 ?0 ?0 10 ?0db ?0db 0db thd +n ?db frequency ?khz figure 1. thd+n vs. frequency midscale fullscale fullscale 1 10 100 1k 10k 100k hz 400 350 300 250 200 150 100 50 0 nv/ ? hz figure 2. noise density figure 3. broadband noise (20 khz bandwidth, midscale) AD1862N-J gain linearity 0 100 80 60 40 20 digital input ?db 2 1 1 2 analog output error ?db figure 4. gain linearity ?0 ?0 ?0 ?0 ?0 ?0 ?0 thd n ?db + ?0db 0db ?0db ?5 0 25 50 75 temperature ?? figure 5. thd+n vs. temperature (1 khz) figure 6. midscale differential linearity
ad1862 C4C rev. a absolute maximum ratings* v l to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +13.2 v Cv l to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cv s to 0 v v s to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +13.2 v Cv s to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C13.2 to 0 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 to +0.3 v digital inputs to dgnd . . . . . . . . . . . . . . . . . . . . . C0.3 to v l soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300 c, 10 sec storage temperature . . . . . . . . . . . . . . . . . . C60 c to +100 c *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1862 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin configuration pin designations pin function description 1 1Cv s bias capacitor 1 2Cv s analog negative supply 1 3 trim trim pot connection 1 4+v l positive logic supply 1 5 clk external clock input 1 6 le latch enable input 1 7 d data input 1 8Cv l negative logic supply 1 9 dgnd digital ground 10 r f feedback resistor 11 i out output current 12 agnd analog ground 13 nr 1 reference capacitor 14 adj midscale adjust 15 nr 2 bias capacitor 16 +v s positive analog supply ordering guide operating temperature package model range thd+n @ fs snr option* ad1862n C25 c to +70 c C92 db, 0.0025% 110 db n-16 AD1862N-J C25 c to +70 c C96 db, 0.0016% 113 db n-16 *n = plastic dip. ad1862 top view (not to scale) 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 ? s trim +v l clk le data nr 2 adj nr 1 agnd i out r f dgnd ? s ? l +v s
ad1862 C5C rev. a total harmonic distortion + noise total harmonic distortion plus noise (thd+n) is defined as the ratio of the square root of the sum of the squares of the val- ues of the harmonics and noise to the value of the fundamental input frequency. it is usually expressed in percent (%) or deci- bels (db). d-range distortion d-range distortion is the ratio of the signal amplitude to the distortion plus noise at C60 db. in this case, an a-weight filter is used. the value specified for d-range performance is the ra- tio measured plus 60 db. settling time settling time is the time required for the output to reach and remain within 1/2 lsb about its final value, measured from the digital input transition. it is a primary measure of dynamic performance and is usually expressed in nanoseconds (ns). signal-to-noise ratio the signal-to-noise ratio is defined as the ratio of the ampli- tude of the output with full-scale present to the amplitude of the output when no signal is present. it is expressed in decibels (db) and measured using an a-weight filter. gain linearity gain linearity is a measure of the deviation of the actual output amplitude from the ideal output amplitude. it is determined by measuring the amplitude of the output signal as the amplitude of that output signal is digitally reduced to a low level. a perfect d/a converter exhibits no difference between the ideal and ac- tual amplitudes. gain linearity is expressed in decibels (db). midscale error midscale error, or bipolar zero error, is the deviation of the ac- tual analog output from the ideal output when the 2s comple- ment input code representing midscale is loaded in the input register. the ad1862 is a current output d/a converter. there- fore, this error is expressed in m a. decoder and digital offset 20-bit dac latch serial input register trim adj feedback register current output v l + nr1 v s agnd v ref nr2 v l latch enable clock data dgnd ad1862 block diagram functional description the ad1862 is a high performance, monolithic 20-bit audio dac. each device includes a voltage reference, a 20-bit dac, 20-bit input latch and a 20-bit serial-to-parallel input register. a special digital offset circuit, combined with segmentation cir- cuitry, produces excellent thd+n and d-range performance. extensive noise-reduction features are utilized to make the noise performance of the ad1862 as high as possible. for example, the voltage reference circuit is a low-noise, 9 volt bandgap cell. this cell supplies the reference voltage to the bipolar offset cir- cuit and the dac. an external noise-reduction capacitor is con- nected to nr1 to form a low-pass filter network. additional noise-reduction techniques are used in the control amplifier of the dac. by connecting an external noise-reduction capacitor to nr2 output noise contributions from the control portion of the dac are similarly reduced. the noise-reduction efforts result in a signal-to-noise ratio of 120 db. the design of the ad1862 uses a combination of segmented de- coder, r-2r topology and digital offset to produce low distor- tion at all signal amplitudes. the digital offset technique shifts the midscale output voltage (0 v) away from the msb transition of the device. therefore, small amplitude signals are not af- fected by an msb change. an extra dac cell is included to avoid clipping the output at full scale. the dac supplies a 1 ma output current to an external i-to-v converter. an on-board 3 k w feedback resistor is also supplied. both the output current and feedback resistor are laser-trimmed to 2% tolerance, simplifying the selection of external filter and/or deemphasis network components. the in- put register and serial-to-parallel converter are fabricated with cmos logic gates. these gates allow the achievement of fast switching speeds and low power consumption. internal ttl- to-cmos converters are used to insure ttl and 5 v cmos compatibility.
ad1862 C6C rev. a analog circuit considerations grounding recommendations the ad1862 has two ground pins, designated analog ground (agnd) and digital ground (dgnd). the analog ground pin is the high-quality ground reference for the device. the ana- log ground pin should be connected to the analog common point in the system. the reference bypass capacitor, the nonin- verting terminal of the current-to-voltage conversion op amp, and any output loads should be connected to this point. the digital ground pin returns ground current from the digital logic portions of the ad1862 circuitry. this pin should be connected to the digital common point in the system. as illustrated in figure 7, agnd and dgnd should be con- nected together at one point in the system. ad1862 top view (not to scale) 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 dgnd agnd figure 7. grounding and bypassing recommendations power supplies and decoupling the ad1862 has four power supply input pins. v s provide the supply voltages which operate the linear portions of the dac in- cluding the voltage reference and control amplifier. the v s supplies are designed to operate with 12 volts. the v l supplies operate the digital portions of the chip includ- ing the input shift register, the input latching circuitry and the ttl-to-cmos level shifters. the v l supplies are designed to be operated from 5 v to 12 v supplies subject only to the limitation that Cv l may not be more negative than Cv s . decoupling capacitors should be used on all power supply input pins. good engineering practice suggests that these capacitors be placed as close as possible to the package pins and the com- mon points. the logic supplies, v l , should be decoupled to dgnd and the analog supplies, v s , should be decoupled to agnd. external noise reduction components two external capacitors are required to achieve low-noise opera- tion. their correct connection is illustrated in figure 8. capacitor c1 is connected between the pin labeled nr1 and analog com- mon. c1 forms a low-pass filter element which reduces noise con- tributed by the voltage reference circuitry. the proper choice for this capacitor is a tantalum type with value of 10 m f or more. this capacitor should be connected to the package pins as closely as possible. this will minimize the effects of parasitic inductance of the leads and connections circuit connections. ?2v analog supply c2 c1 ad1862 top view (not to scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + + note: pin 1 is "high quality" return for bias cap. figure 8. noise reduction capacitors capacitor c2 is connected between the pin labeled nr2 and the negative analog supply, Cv s . this capacitor reduces the portion of output noise contributed by the control amplifier circuitry. c2 should be chosen to be a tantalum capacitor with a value of about 1 m f. again, the connections between the ad1862 and c2 should be made as short as possible. the recommended values for c1 and c2 are 10 m f and 1 m f, respectively. the ratio between c1 and c2 should be approxi- mately 10. additional noise reduction can be gained by choos- ing slightly higher values for c1 and c2 such as 22 m f and 2.2 m f. figure 2 illustrates the noise performance of the ad1862 with 10 m f and 1 m f. external amplifier connections the ad1862 is a current-output d/a converter. therefore, an external amplifier, in combination with the on-board feedback resistor, is required to derive an output voltage. figure 9 illus- trates the proper connections for an external operational ampli- fier. the output of the ad1862 is intended to drive the summing junction of an external current-to-voltage conversion op amp. therefore, the voltage on the output current pin of the ad1862 should be approximately the same as that on the agnd pin of the device. the on-board 3 k w feedback resistor and the 1 ma output current typically have 1% tolerance or less. this makes the choice of external components very simple and eliminates addi- tional trimming. for example, if a user wishes to derive an out- put voltage higher than the 3 v swing offered by the output current and feedback resistor combination, all that is required is to combine a standard value resistor with the feedback resistor to achieve the appropriate output voltage swing. this technique can be extended to include the choice of elements in the deemphasis network, etc.
total harmonic distortion + noise the thd figure of an audio dac represents the amount of un- desirable signal produced during reconstruction and playback of an audio waveform. the thd specification, therefore, provides a direct method to classify and choose an audio dac for a de- sired level of performance. by combining noise measurement with the thd measurement, a thd+n specification is realized. this specification indicates all of the undesirable signal produced by the dac, including harmonic products of the test tone as well as noise. analog devices tests all ad1862s on the basis of thd+n per- formance. in this test procedure, a digital data stream represent- ing a 0 db, C20 db or C60 db sine wave is sent to the device under test. the frequency of the waveform is 990.5 hz. input data is sent to the ad1862 at an 8 f s rate (352.8 khz). the ad1862 under test produces an output current which is con- verted to an output voltage by an external amplifier. figure 10 illustrates the recommended test circuit. deglitchers and trims are not used during this test procedure. the automatic test equipment digitizes 4096 samples of the output test waveform, incorporating 23 complete cycles of the sine wave. a 4096 point fft is performed on the test data. v out ad1862 top view (not to scale) 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 figure 9. external amplifier connections based upon the harmonics of the fundamental 990.5 hz test tone, and the noise components in the audio band, the total har- monic distortion + noise of the device is calculated. the ad1862 is available in two performance grades. the ad1862n produces a maximum of 0.0025% thd+n at 0 db signal lev- els. the higher performance AD1862N-J produces a maximum of 0.0016% thd+n at 0 db signal levels. signal-to-noise ratio the signal-to-noise ratio (snr) of the ad1862 is tested in the following manner. the amplitude of a 0 db signal is measured. the device under test is then set to midscale output voltage (0 volts). the amplitude of all noise present to 30 khz is mea- sured. the snr is the ratio of these two measurements. the snr figure for the ad1862 includes the output noise contrib- uted by the ne5534 op amp used in the test fixture but does not include the noise contributed by the low-pass filter used in the test fixture. the ad1862n has a minimum snr of 110 db. the higher performance AD1862N-J has a minimum snr of 113 db. testing the ad1862 rev. a C7C ad1862 top view (not to scale) 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 0.1 m f 0.1 m f 0.1 m f 0.1 m f 10 m f 1 m f 3-pole low pass filter 12v 12v 12v 17mhz 352.8khz digital common se5534a output voltage analog common 12v 360pf + + figure 10. recommended test circuit
ad1862 C8C rev. a optional trim adjustment the ad1862 includes an external midscale adjust feature. should an application require improved distortion performance under small and very small signal amplitudes (C60 db and lower), an adjustment is possible. two resistors and one poten- tiometer form the adjustment network. figure 11 illustrates the correct configuration of the external components. analog devices recommends that this adjustment be performed with C60 db signal amplitudes or lower. minor performance im- provement is achieved with larger signal amplitudes such as C20 db. almost no improvement is possible when this adjust- ment is performed with 0 db signal amplitudes. 470k w 470k w 100k w ad1862 top view (not to scale) 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 12v figure 11. external midscale adjust digital circuit considerations input data data is transmitted to the ad1862 in a bit stream composed of 20-bit words with a serial, 2s complement, msb first format. three signals must be present to achieve proper operation. they are the data, clock and latch enable signals. input data bits are clocked into the input register on the rising edge of the clock signal (clk). the lsb is clocked in on the 20th clock pulse. when all data bits are loaded, a low going latch enable (le) pulse updates the dac input. figure 12a illustrates the general signal requirements for data transfer for the ad1862. msb word n lsb msb word n+1 data clock latch enable figure 12a. input data timing figure 12b illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished success- fully. the input pins of the ad1862 are both ttl and 5 v cmos compatible, independent of the power supplies used in the application. the input requirements illustrated in figure 12b are compatible with the data outputs provided by popular digital interpolation filter chips used in digital audio playback systems. the ad1862 input clock will run at 17 mhz allowing data to be transferred at a rate of 16 f s . of course, it will also function at slower rates such as 2 , 4 or 8 f s . >15ns >15ns bits clocked to shift register clk > 60ns >15ns >25ns >25ns data latch enable (le) >60ns >40ns internal dac input register updated with 20 most recent bits 2nd bit lsb (20th bit) word next >40ns >40ns msb 1st bit figure 12b. timing requirements
ad1862 C9C rev. a the ad1862 is an extremely high performance dac designed for high-end consumer and professional digital audio applica- tions. compact disc players, digital preamplifiers, digital musi- cal instruments and sound processors benefit from the extended dynamic range, low thd+noise and high signal-to-noise ratio. for the first time, the d/a converter is no longer the basic limi- tation in the performance of a cd player. the performance of professional audio gear, such as mixing consoles, digital tape recorders and multivoice synthesizers can utilize the wide dynamic range and signal-to-noise ratio to achieve greater performance. and, the ad1862s space saving 16-pin package contributes to compact system design. this per- mits a system designer to incorporate more voices in multivoice synthesizers, more tracks in multitrack tape recorders and more channels in multichannel mixing consoles. furthermore, high-resolution signal processing and waveform generation applications are equally well served by the ad1862. high performance cd player figure 13 illustrates the application of ad1862s in a high per- formance cd player. two ad1862s are used, one for the left channel and one for the right channel. the cxd11xx chip de- codes the digital data coming from the read electronics and sends it to the sm5813. input data is sent to each ad1862 by the sm5813 digital interpolating filter. this device operates at 8 times oversampling. the ne5534 op amps are chosen for current-to-voltage converters due to their low distortion and low noise. the output filters are 5-pole designs. for the purpose of clarity, all bypass capacitors have been omitted from the schematic. 5v digital supply ne5534 left channel output right channel output 5v digital supply 16.9344mhz xti xto dol cko bcko wcko dor bcki din lrci sm5813 xtai lrck data c210 slob pssl sony cxd1125 1130 1135 ow20 ckdv low pass filter 10 m f 1 m f 12v analog supply 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 low pass filter 10 m f 1 m f 12v analog supply 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 12v analog supply ne5534 + + + + v + l le v s trim clk data v l v s v + s nr 2 adj nr 1 agnd i out r f dgnd ad1862 ad1862 v + s nr 2 adj nr 1 agnd i out r f dgnd v + l le v s trim clk data v l v s figure 13. high performance 20-bit 8 oversampling cd player application
ad1862 C10C rev. a high-resolution signal processing figure 14 illustrates the ad1862 combined with the dsp56000. in high-resolution applications, the combination of the 24-bit architecture of the dsp56000 and the low noise and high reso- lution of the ad1862 can produce a high-resolution, low-noise system. as shown in figure 14, the clock signal supplied by the dsp processor must be inverted to be compatible with the input of the ad1862. the exact architecture of the output low-pass filter depends on the sample rate of the output data. in general, the higher the oversampling rate, the fewer number of filter poles are required to prevent aliasing. the 20-bit resolution is particularly suitable for professional au- dio, mixing or equalization equipment. its resolution allows 24 db of equalization to be performed on 16-bit input words without signal truncation. furthermore, up to sixteen 16-bit in- put words can be mixed and output directly to the ad1862. in this case, no loss of signal information would be encountered. 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 low pass filter output voltage 0.1 m f 0.1 m f 0.1 m f 5v digital supply 12v analog supply 12v analog supply 0.1 m f 10 m f ad846 analog common digital common 5v digital supply v cc sck sc2 std v dd dsp56001 1 m f ad1862 v + s nr 2 adj nr 1 agnd i out r f dgnd v + l le v s trim clk data v l v s figure 14. dsp56001 and ad1862 produce high resolution signal processing system
ad1862 C11C rev. a other digital audio components available from analog devices ad1856 16-bit audio dac complete, no external components required 0.0025% thd low cost 16-pin dip or soic package standard pinout ad1860 18-bit audio dac complete, no external components required 0.002% thd+n 108 db signal-to-noise ratio 16-pin dip or soic package ad1864 dual 18-bit audio dac complete, no external components 0.002% thd+n 115 db channel separation 24-pin dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16-bit latch 16-bit dac serial input register control logic ad1856 i out v s dgnd nc clk le data v l v l + nc no connect = v s + trim msb adj i out agnd sj r f v out nc no connect = 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18-bit latch 18-bit dac serial input register control logic ad1860 i out v s dgnd nc clk le data v l + v s + trim msb adj i out agnd sj r f v out v l v s 1 2 3 4 5 6 7 8 9 10 11 12 trim msb i out agnd sj r f v out v + l dr lr ck 18-bit latch reference 20 18-bit latch dgnd v l v s + trim msb i out agnd sj r f v out 13 14 15 16 dl ll 17 18 19 21 22 23 24 reference 18-bit dac 18-bit dac ad1864
ad1862 C12C rev. a outline dimensions dimensions shown in inches and (mm). c1445C7C9/90 printed in u.s.a. plastic dip (n-16)

▲Up To Search▲

Price & Availability of AD1862N-J

	To Download AD1862N-J Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .